CS 451/551

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CS 451/551: Advanced Computer Architecture

Catalog Description: Principles and alternatives in instruction set design; processor implementation techniques, pipelining, parallel processors, memory hierarchy, and input/output; measurement of performance and cost/performance trade-off.

Type: CS 451 is a Technical Elective for CS majors. CS 551 is available for graduate credit. Cross-listed with ECE 441/541.

Total Credits: 3

Course Coordinator: Robert Rinker

URL: http://www2.cs.uidaho.edu/~rinker/cs451

Prereq: CS 150, Stat 301, or permission

Textbook: John Hennessy and David Patterson, Computer Architecture - A Quantitative Approach, 5th Ed, Morgan Kaufmann, 2012, or equivalent text.

Major Topics Covered

  • Pipelining concepts
  • Instruction-level parallelism
  • Dynamic scheduling
  • Limits on ILP
  • Exploiting ILP with software
  • Memory hierarchy and caches
  • Virtual memory
  • Memory performance optimization
  • Multiprocessors - thread level parallelism
  • Storage systems
  • Interconnection networks and clusters

Course Outcomes

At the conclusion of this course, the student should be able to:

  1. Classify processors by architecture type
  2. Describe how memory cache functions
  3. Analyze the tradeoffs in cache design, and select and optimal design for a particular application
  4. Understand the issues and tradeoffs in instruction pipelining
  5. Understand non-pipelined instruction-level parallelism, e.g. Tomasulo's algorithm
  6. Understand and describe practical issues in parallel computing, such as
    • Thread-level parallelism
    • Cache coherence
  7. Analyze input/output devices for performance: interconnection networks, redundant array of independent disks (RAID).